TTU Develop a Verilog Model for The Pipelined RISC CPU Computer Science Task

Description

Page 32-40 from the book is needed for the assignment.

I need to implement a pipelined RISC architecture CPU (the figure is given in the book). The instructions are 32 bits long, the register file has 32 registers each 32 bit long. There 27 core instructions and a 7 bit OPCODE. 

I have the ALU implemented (attached) and I need  the rest of the modules (register file, instruction decoder, and instruction memory) and the entire architecture in Verilog.

srcs/sources_1/new?fbclid=IwAR2adfT_rVGbr8hC9F2i3-X00Q63Wxy9lJMMqCpZFxvmRXk02BP5fXQY_YQ”>https://github.com/JacobSiau/MPA_RISC/tree/master/mpa.srcs/sources_1/new?fbclid=IwAR2adfT_rVGbr8hC9F2i3-X00Q63Wxy9lJMMqCpZFxvmRXk02BP5fXQY_YQ